This invention relates generally to image sensors, and more particularly, to back-side illuminated (BSI) image sensors.
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of an integration cycle, collected charge is converted into a voltage, which is supplied to output terminals of the sensor.
For active pixel image sensors, charge-to-voltage conversion is performed in the pixels themselves. Pixel signals can be transferred as analog signals from individual pixels to output terminals of the image sensor. Alternatively, an analog pixel signal can be converted into a digital signal before it is transferred to the output terminals of the image sensor.
Various pixel addressing and scanning schemes can be used to transfer pixel signals from the individual pixels to the image sensor output terminals. Typically, each pixel has a buffer amplifier, such as a source follower (SF) transistor, which can drive sense lines that are connected to the pixels by suitable addressing transistors.
After pixel signals have been transferred out from the pixels, the pixels are reset in order to be ready for the accumulation of new charge. In pixels that have floating diffusion (FD) nodes that serve as charge detection nodes, the reset can be accomplished by momentarily turning on a reset transistor that conductively connects the floating diffusion node to a reference voltage supply, which is typically a pixel drain node. Resetting a pixel removes collected charge in the floating diffusion node of the pixel.
However, pixel reset may be accompanied by noise called reset noise, also known as kTC noise. Techniques such as correlated double sampling (CDS) signal processing techniques are used to reduce kTC noise in the signal. Typical active pixel sensors that utilize CDS signal processing techniques usually have three transistors per pixel (3T pixels) or 4 transistors per pixel (4T pixels). Some of the pixel transistors can be shared amongst several pixels.
A cross-sectional view of a conventional pixel 100 is shown in FIG. 1. Pixel 100 may be formed in a substrate 101. A p+ type layer 102 is deposited on a back surface of substrate 101, which prevents generation of excessive dark current by interface states. A p-type epitaxial layer 115 is formed over p+ layer 102. A photodiode PD (in region 96) is formed by n-type region 108 (also known as a charge storage layer) and p+ type pinning layer 107.
Pixel 100 has a transfer gate 110 that receives transfer signal Tx. Transfer gate Tx 110 is formed from doped polysilicon. An oxide layer 109 isolates transfer gate 110 from epitaxial layer 115. A masking oxide 111 is formed over transfer gate 110 that serves as a patterning hard mask as well as an additional blocking mask for ion plantation. Sidewall spacers 116 can help to control mutual edge positions of p+ type layer 107 and n-type region 108. Floating diffusion 104 is formed in p-well 103 and receives charge signal from PD.
P+ type regions 105 and 106 provide isolation between pixels and can be connected to ground GND. Inter-level (IL) oxide layers 112 are used for isolation of multi-level metal wiring and interconnect. Metal vias 114 in contact holes 113 connect pixel active circuit components such as isolation regions 105 and 106, transfer gate 110, and floating diffusion 104 to metal wiring.
Transfer gate Tx 110, having a length as marked by arrows 98, occupies a large portion of valuable area of pixel 100. Transistors such as a source-follower (SF) transistor, reset transistor, and addressing transistor, while not shown in FIG. 1, also occupy valuable pixel area.
It would be desirable to have improved pixel circuits that are having less transistor gate surface area in order to maximize pixel area that is used for charge storage, thereby increasing the pixel charge storage capacity.